// (C) 2022 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other 
// software and tools, and its AMPP partner logic functions, and any output 
// files from any of the foregoing (including device programming or simulation 
// files), and any associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License Subscription 
// Agreement, Intel FPGA IP License Agreement, or other applicable 
// license agreement, including, without limitation, that your use is for the 
// sole purpose of programming logic devices manufactured by Intel and sold by 
// Intel or its authorized distributors.  Please refer to the applicable 
// agreement for further details.

`include "mainfpga_version.vh"

module bnc_cpu_mem_seq
(
    input           iClk,
    input           iRst_n,
    input           iCPU_PWR_EN,                        // From master_fub, enable CPU main power domain and memory power domain
    input           iENABLE_TIME_OUT,                   // Assign value, HIGH to enable 500us timeout watchdog
    input           iFM_INTR_PRSNT_N,                   // Indicate interposer present
    input           iFM_CPU_SKTOCC_N,                   // From CPU, indicate socket occupy
    input           iINTR_ID,                           // Indicate Interposer type A (LOW) or B (HIGH)
    input           iPWRGD_PVCCFA_EHV_CPU,              // CPU VR PWRGD PVCCFA_EHV
    input           iPWRGD_PVCCFA_EHV_FIVRA_CPU,        // From VCCFA_EHV_FIVRA VR, indicate this VR is fully on
    input           iPWRGD_PVCCINFAON_CPU,              // From VCCINFAON VR, indicate this VR is fully on
    input           iPWRGD_P1V0_AUX,                    // to power IO bank of fpga before or at same time as VNN.
    input           iPWRGD_PVNN_MAIN_CPU,               // CPU VR PWRGD PVNN
    input           iPWRGD_P1V1_AUX,                    // to power IO bank of fpga before or at same time as VCCD_HV.
    input           iPWRGD_PVCCD0_HV_CPU,               // From VCCD0_HV VR, indicate this VR is fully on
    input           iPWRGD_PVCCD1_HV_CPU,               // From VCCD1_HV VR, indicate this VR is fully on
    input           iPWRGD_PVCCIN_CPU,                  // From VCCIN VR, indicate this VR is fully on
    input           iclear_error_state,                 // From master_fub, indicate BMC force to exit error state

    output reg      oMEM_PWR_FLT,                       // To BMC through LVDS and sGPIO, indicate VR failure on DIMM
    output reg      oMEM_PWR_OK,                        // To ddr5_pwrgd_logic, indicate valid DIMM PWRGD for DIMM failure detection

    output reg      oFM_PVCCFA_EHV_CPU_EN, 			    //CPU VR EN PVCCFA_EHV
    output reg      oFM_P1V0_AUX_EN,                    //to power IO bank of fpga before or at same time as VNN.
    output reg      oFM_PVNN_MAIN_CPU_EN, 				//CPU VR EN PVNN
    output reg      oFM_PVCCFA_EHV_FIVRA_CPU_EN,        // To VCCFA_EHV_FIVRA VR, enable this VR
    output reg      oFM_PVCCINFAON_CPU_EN,              // To VCCINFAON VR, enable this VR
    output reg      oFM_P1V1_AUX_EN,                    // to power IO bank of fpga before or at same time as VCCD_HV
    output reg      oFM_PVCCD_HV_CPU_EN,                // To VCCD_HV VRs, enable PVCCD0 and PVCCD1 VRs with the same signal
    output reg      oFM_PVCCIN_CPU_EN,                  // To VCCIN VR, enable this VR
    output reg      oVR_PWROFF_TIMEOUT_ERR,             // To master_fub, indicate timeout error during certain VR power off
    output reg      oFM_PVCC3V3_AUX_CPU_EN,             // To CPU1, enabled this VR in S0 state

    output reg      oCPU_PWR_OK,                        // To master_fub, indicate all VRs of CPU main domain are on 
    output reg      oCPU_PWR_FLT,                       // To master_fub, indicate CPU main VR failure

    output reg      oCPU_PWR_FLT_EHV_CPU, 				//Fault  PVCCFA_EHV
    output reg      oCPU_PWR_FLT_PVNN, 					//Fault  PVNN
    output reg      oCPU_PWR_FLT_EHV_FIVRA_CPU,         // To debug FPGA through sGPIO, indicate error source is VCCFA_EHV_FIVRA
    output reg      oCPU_PWR_FLT_PVCCINFAON_CPU,        // To debug FPGA through sGPIO, indicate error source is VCCINFAON
    output reg      oCPU_PWR_FLT_PVCCIN,                // To debug FPGA through sGPIO, indicate error source is VCCIN
    output reg      oCPU_PWR_FLT_PVCCD0_HV,             // To debug FPGA through sGPIO, indicate error source is VCCD0_HV
    output reg      oCPU_PWR_FLT_PVCCD1_HV              // To debug FPGA through sGPIO, indicate error source is VCCD1_HV
);

/*************************************************************************************************************
 * Local Parameter Definitions                                                                               *
 *************************************************************************************************************/
   localparam  LOW  = 1'b0;
   localparam  HIGH = 1'b1;

    `ifdef SIMULATION
        localparam  T_500uS_2M  =  11'd1000;
        localparam  T_100mS_2M  =  11'd1000;
    `else
        localparam  T_500uS_2M  =  11'd1000;
        localparam  T_100mS_2M  =  19'd200000;
    `endif

    localparam  ST_INIT                 = 4'd0;
    localparam  ST_PVCCD_HV             = 4'd1;
    localparam  ST_PVCCFA_EHV_FIVRA     = 4'd2;
    localparam  ST_PVCCINFAON           = 4'd3;
    localparam  ST_PVCCIN               = 4'd4;
    localparam  ST_CPUDONE              = 4'd5;
    localparam  ST_PWR_DOWN             = 4'd6;
    localparam  ST_PVCCIN_OFF           = 4'd7;
    localparam  ST_PVCCINFAON_OFF       = 4'd8;
    localparam  ST_PVCCFA_EHV_FIVRA_OFF = 4'd9;
    localparam  ST_PVCCD_HV_OFF         = 4'd10;
    localparam  ST_PWROFF_TIMEOUT       = 4'd11;
    localparam  ST_PVNN                 = 4'd12;
    localparam  ST_PVNN_OFF             = 4'd13;

/*************************************************************************************************************
 * Local Registers and Wires Definitions                                                                     *
 *************************************************************************************************************/
   reg [3:0]        root_state;                             // VR main sequence state machine
   reg [3:0]        rPREVIOUS_STATE = ST_INIT;              // VR previous sequene state machine

   reg              rPWRGD_PVCCFA_EHV_FIVRA_CPU;
   reg              rPWRGD_PVCCINFAON_CPU;
   reg              rPWRGD_PVCCIN_CPU;
   reg              rPWRGD_PVCCD0_HV_MEM;
   reg              rPWRGD_PVCCD1_HV_MEM;
   reg              rPWRGD_PVCCFA_EHV_CPU;
   reg              rPWRGD_PVNN_MAIN_CPU;
   reg              rStart100msTimer;
   
   wire             wTIME_OUT_500uS;                        // 500 uS delay to turn on CPU
   wire             wDLY_500uS;
   wire             wCNT_RST_N;
   wire             wStart100msTimer;                       // 100 ms delay to turn off each VR
   wire             wDoneTimer100ms;

/*************************************************************************************************************
 * Logic                                                                                                     *
 *************************************************************************************************************/
    assign      wCNT_RST_N              = (root_state == rPREVIOUS_STATE) ? HIGH : LOW;
    assign      wTIME_OUT_500uS         = wDLY_500uS && wCNT_RST_N && iENABLE_TIME_OUT;
    assign      wStart100msTimer        = rStart100msTimer;

    
    always @ (posedge iClk or negedge iRst_n)
    begin
        if (!iRst_n) 
        begin
            oFM_PVCC3V3_AUX_CPU_EN      <= LOW;
        end
        else 
        begin
            if(!iFM_INTR_PRSNT_N) //if interposer present, this signal is always high
            begin
                oFM_PVCC3V3_AUX_CPU_EN      <= HIGH;
            end
            else if (iCPU_PWR_EN)//if no interposer, wait for cpu pwr en and assert it
            begin
                oFM_PVCC3V3_AUX_CPU_EN      <= HIGH;
            end
            else
            begin
                oFM_PVCC3V3_AUX_CPU_EN      <= oFM_PVCC3V3_AUX_CPU_EN;
            end
        end
    end

    // Only for non-legacy CPU. This rail of legacy CPU is controlled by board

    always @ (posedge iClk or negedge iRst_n) begin                                         // CPU main VRs and Memory VRs Control Logic
        if (!iRst_n) begin
           oFM_PVCCFA_EHV_FIVRA_CPU_EN <= LOW;
           oFM_PVCCFA_EHV_CPU_EN       <= LOW;
           oFM_PVCCINFAON_CPU_EN       <= LOW;
           oFM_P1V1_AUX_EN             <= LOW;
           oFM_PVCCD_HV_CPU_EN         <= LOW;
           oFM_P1V0_AUX_EN             <= LOW;
           oFM_PVNN_MAIN_CPU_EN        <= LOW;
           oFM_PVCCIN_CPU_EN           <= LOW;
           oVR_PWROFF_TIMEOUT_ERR      <= LOW;
           oCPU_PWR_OK                 <= LOW;
           oMEM_PWR_OK                 <= LOW;
           rStart100msTimer            <= LOW;
           root_state                  <= ST_INIT;
        end
        
	else begin
            rPREVIOUS_STATE             <= root_state; 
            if(!iFM_CPU_SKTOCC_N) 
            begin                                                     // Verify if CPU interposer is present
                case (root_state)
                    ST_INIT: begin                                                          // Initial state
                        oMEM_PWR_OK                     <= LOW;
                        oCPU_PWR_OK                     <= LOW;
                        if (iCPU_PWR_EN && !oCPU_PWR_FLT && !oMEM_PWR_FLT) begin            // master_fub ask to turn on CPU main power domain and memory power domain
                           oFM_P1V1_AUX_EN             <= HIGH;                             
                           root_state                  <= ST_PVCCD_HV;
                        end
                    end // case: ST_INIT

                    ST_PVCCD_HV: begin                                                      // Turn on VCCD_HV VR for DDR5 memory controller support
                        oFM_PVCCD_HV_CPU_EN             <= HIGH;
                        oFM_P1V1_AUX_EN                 <= HIGH;
                        if (!iCPU_PWR_EN || oCPU_PWR_FLT || wTIME_OUT_500uS) begin          // Power off or power failure or timeout, turn off memory VRs
                            root_state <= ST_PVCCIN_OFF;                                    
                        end else if (iPWRGD_PVCCD0_HV_CPU && iPWRGD_PVCCD1_HV_CPU && iPWRGD_P1V1_AUX) begin
                            root_state                  <= ST_PVCCFA_EHV_FIVRA;             // VCCD VR already turned on, go to next stage
                        end
                    end // case: ST_PVCCD_HV

                    ST_PVCCFA_EHV_FIVRA: begin                                              // Turn on VCCFA_EHV_FIVRA VR for FIVR domain support
                        oMEM_PWR_OK                     <= HIGH;                            // Memory VRs already on
                        oFM_PVCCFA_EHV_FIVRA_CPU_EN     <= HIGH;
                       
                        if (!iFM_INTR_PRSNT_N)
                          oFM_PVCCFA_EHV_CPU_EN         <= HIGH;
                        else
                          oFM_PVCCFA_EHV_CPU_EN         <= LOW;
                       
                        if (!iCPU_PWR_EN || oCPU_PWR_FLT || wTIME_OUT_500uS) begin          // Power off or power failure or timeout, turn off memory VRs
                            root_state                  <= ST_PVCCIN_OFF;   
                        end else if (iPWRGD_PVCCFA_EHV_FIVRA_CPU && (iPWRGD_PVCCFA_EHV_CPU || iFM_INTR_PRSNT_N)) begin
                            root_state                  <= ST_PVCCINFAON;                   // VCCFA_EHV_FIVRA VR already turned on, go to next stage
                        end
                    end // case: ST_PVCCFA_EHV_FIVRA

                    ST_PVCCINFAON: begin                                                    // Turn on VCCINFAON VR for early domain, including FIVR boot
                        oFM_PVCCINFAON_CPU_EN           <= HIGH;
                        if (!iCPU_PWR_EN || oCPU_PWR_FLT || wTIME_OUT_500uS) begin          // Power off or power failure or timeout, turn off memory VRs
                            root_state                  <= ST_PVCCIN_OFF;
                        end else if (iPWRGD_PVCCINFAON_CPU && iFM_INTR_PRSNT_N) begin
                            root_state                  <= ST_PVCCIN;                       // VCCINFAON VR already turned on, go to next stage
                        end else if (iPWRGD_PVCCINFAON_CPU && !iFM_INTR_PRSNT_N) begin
                            root_state                  <= ST_PVNN;
                            oFM_P1V0_AUX_EN             <= HIGH;
                        end
                    end // case: ST_PVCCINFAON

                    ST_PVNN: begin
                       oFM_PVNN_MAIN_CPU_EN            <= HIGH;
                       oFM_P1V0_AUX_EN                 <= HIGH;
                       if(!iCPU_PWR_EN || oCPU_PWR_FLT || wTIME_OUT_500uS) begin           // Power off or power failure or timeout, turn off memory VRs
                          root_state                   <= ST_PVCCIN_OFF;
                       end else if (iPWRGD_PVNN_MAIN_CPU) begin
                          root_state                   <= ST_PVCCIN;
                       end
                    end

                    ST_PVCCIN: begin                                                        // Turn on VCCIN VR for main power supply support
                        oFM_PVCCIN_CPU_EN               <= HIGH;
                        if(!iCPU_PWR_EN || oCPU_PWR_FLT || wTIME_OUT_500uS) begin           // Power off or power failure or timeout, turn off memory VRs
                            root_state                  <= ST_PVCCIN_OFF;
                        end else if (iPWRGD_PVCCIN_CPU) begin
                            root_state                  <= ST_CPUDONE;                      // VCCIN VR already turned on, all CPU main VRs and memory VRs turned on
                        end 
                    end // case: ST_PVCCIN

                    ST_CPUDONE: begin                                                       // Indicate all CPU main domain and memory power domain are on
                        oCPU_PWR_OK                     <= HIGH;                            // CPU VRs already on
                        if((!iCPU_PWR_EN) ||  oCPU_PWR_FLT) begin
                            root_state                  <= ST_PVCCIN_OFF;                   // Power off or power failure, turn off memory VRs
                        end 
                    end // case: ST_CPUDONE

                    ST_PVCCIN_OFF: begin                                                    // Turn off VCCIN VR
                        oFM_PVCCIN_CPU_EN               <= LOW;
                        rStart100msTimer                <= HIGH;                            // Start 100 ms watchdog
                        if (iPWRGD_PVCCIN_CPU && wDoneTimer100ms) begin                     // Timeout when turning off VCCIN VR
                            root_state                  <= ST_PWROFF_TIMEOUT;
                        end else if (!iPWRGD_PVCCIN_CPU && iFM_INTR_PRSNT_N) begin          // VCCIN VR already turned off, go to next stage
                            rStart100msTimer            <= LOW;                             // Clear watchdog
                            root_state                  <= ST_PVCCINFAON_OFF;
                        end else if (!iPWRGD_PVCCIN_CPU && !iFM_INTR_PRSNT_N) begin
                            rStart100msTimer            <= LOW;                             
                            root_state                  <= ST_PVNN_OFF;
                        end
                    end // case: ST_PVCCIN_OFF

                    ST_PVNN_OFF: begin
                       oFM_PVNN_MAIN_CPU_EN             <= LOW;
                       oFM_P1V0_AUX_EN                  <= LOW;
                       if (iPWRGD_PVNN_MAIN_CPU && wDoneTimer100ms) begin
                          root_state                    <= ST_PWROFF_TIMEOUT;
                       end else if (!iPWRGD_PVNN_MAIN_CPU) begin
                          rStart100msTimer              <= LOW;
                          root_state                    <= ST_PVCCINFAON_OFF;
                       end
                    end //case: ST_PVNN_OFF
                      

                    ST_PVCCINFAON_OFF: begin                                                // Turn off VCCINFAON VR
                       oFM_PVCCINFAON_CPU_EN           <= LOW;
                       rStart100msTimer                <= HIGH;                            // Restart 100 ms watchdog
                       if (iPWRGD_PVCCINFAON_CPU && wDoneTimer100ms) begin                 // Timeout when turning off VCCINFAON VR
                           root_state                  <= ST_PWROFF_TIMEOUT;
                       end else if (!iPWRGD_PVCCINFAON_CPU) begin                          // VCCINFAON VR already turned off, go to next stage
                          rStart100msTimer            <= LOW;                             // Clear watchdog
                          root_state                  <= ST_PVCCFA_EHV_FIVRA_OFF;
                       end
                    end // case: ST_PVCCINFAON_OFF

                    ST_PVCCFA_EHV_FIVRA_OFF: begin                                          // Turn off VCCFA_EHV_FIVRA VR
                        oFM_PVCCFA_EHV_FIVRA_CPU_EN     <= LOW;
                        oFM_PVCCFA_EHV_CPU_EN           <= LOW;
                        rStart100msTimer                <= HIGH;                            // Restart 100 ms watchdog
                        if (iPWRGD_PVCCFA_EHV_FIVRA_CPU && wDoneTimer100ms) begin           // Timeout when turning off VCCFA_EHV_FIVRA VR
                            root_state                  <= ST_PWROFF_TIMEOUT;
                        end else if (!iPWRGD_PVCCFA_EHV_FIVRA_CPU) begin                    // VCCFA_EHV_FIVRA VR already turned off, go to next stage
                            rStart100msTimer            <= LOW;                             // Clear watchdog
                            root_state                  <= ST_PVCCD_HV_OFF;
                            end
                        end // case: ST_PVCCFA_EHV_FIVRAOFF

                    ST_PVCCD_HV_OFF: begin                                                  // Turn off VCCD VR
                        oFM_PVCCD_HV_CPU_EN             <= LOW;
                        oFM_P1V1_AUX_EN                 <= LOW;
                        rStart100msTimer                <= HIGH;                            // Restart 100 ms watchdog
                        if (iPWRGD_PVCCD0_HV_CPU && wDoneTimer100ms) begin                  // Timeout when turning off VCCD VR
                            root_state                  <= ST_PWROFF_TIMEOUT;
                        end else if (!iPWRGD_PVCCD0_HV_CPU) begin                           // All CPU main domain and memory domain already turned off, go to initial state
                            rStart100msTimer            <= LOW;                             // Clear watchdog
                            root_state                  <= ST_INIT;
                        end
                    end // case: ST_PVCCD_HV_OFF

                    ST_PWROFF_TIMEOUT: begin
                        oVR_PWROFF_TIMEOUT_ERR          <= HIGH;
                        oFM_PVCCFA_EHV_FIVRA_CPU_EN     <= LOW;
                        oFM_PVCCFA_EHV_CPU_EN           <= LOW;
                        oFM_PVCCINFAON_CPU_EN           <= LOW;
                        oFM_PVNN_MAIN_CPU_EN            <= LOW;
                        oFM_P1V0_AUX_EN                 <= LOW;
                        oFM_P1V1_AUX_EN                 <= LOW;     //To turn off P1V1_AUX (this will turn PLD IO bank OFF )
                        oFM_PVCCD_HV_CPU_EN             <= LOW;
                        oFM_PVCCIN_CPU_EN               <= LOW;
                        oCPU_PWR_OK                     <= LOW;
                        oMEM_PWR_OK                     <= LOW;
                        rStart100msTimer                <= LOW;
                        if (iclear_error_state) begin                                       // BMC force to exit error state, try to clear VR failure status
                            root_state                  <= ST_INIT;
                            oVR_PWROFF_TIMEOUT_ERR      <= LOW;
                        end
                    end // case: ST_PWROFF_TIMEOUT

                    default: begin
                        oFM_PVCCFA_EHV_FIVRA_CPU_EN     <= LOW;
                        oFM_PVCCFA_EHV_CPU_EN           <= LOW;
                        oFM_PVCCINFAON_CPU_EN           <= LOW;
                        oFM_P1V1_AUX_EN                 <= LOW;     //To turn off P1V1_AUX (this will turn PLD IO bank OFF )
                        oFM_PVCCD_HV_CPU_EN             <= LOW;
                        oFM_PVNN_MAIN_CPU_EN            <= LOW;
                        oFM_P1V0_AUX_EN                 <= LOW;
                        oFM_PVCCIN_CPU_EN               <= LOW;
                        oVR_PWROFF_TIMEOUT_ERR          <= LOW;
                        oCPU_PWR_OK                     <= LOW;
                        oMEM_PWR_OK                     <= LOW;
                        rStart100msTimer                <= LOW;
                        root_state                      <= ST_INIT;
                    end // case: default
                endcase
            end else begin
                root_state <= ST_INIT;
            end
        end
    end

   always @ (posedge iClk, negedge iRst_n) begin                        // CPU main VRs and Memory VRs Fault Logic
        if (!iRst_n) begin
            rPWRGD_PVCCFA_EHV_FIVRA_CPU         <= LOW;
            rPWRGD_PVCCINFAON_CPU               <= LOW;
            rPWRGD_PVCCIN_CPU                   <= LOW;
            rPWRGD_PVCCD0_HV_MEM                <= LOW;
            rPWRGD_PVCCD1_HV_MEM                <= LOW;
            rPWRGD_PVCCFA_EHV_CPU               <= LOW;
            rPWRGD_PVNN_MAIN_CPU                <= LOW;

            oCPU_PWR_FLT_PVCCD0_HV              <= LOW;
            oCPU_PWR_FLT_PVCCD1_HV              <= LOW;
            oCPU_PWR_FLT_EHV_FIVRA_CPU          <= LOW;
            oCPU_PWR_FLT_PVCCINFAON_CPU         <= LOW;
            oCPU_PWR_FLT_PVCCIN                 <= LOW;
            oCPU_PWR_FLT_PVNN                   <= LOW;
            oCPU_PWR_FLT_EHV_CPU                <= LOW;

            oCPU_PWR_FLT                        <= LOW;
            oMEM_PWR_FLT                        <= LOW;
        end

        else begin
            if (iclear_error_state) begin                               // BMC force to exit error state, try to clear VR failure status
                oCPU_PWR_FLT_PVCCD0_HV          <= LOW;
                oCPU_PWR_FLT_PVCCD1_HV          <= LOW;
                oCPU_PWR_FLT_EHV_FIVRA_CPU      <= LOW;
                oCPU_PWR_FLT_PVCCINFAON_CPU     <= LOW;
                oCPU_PWR_FLT_PVCCIN             <= LOW;
                oCPU_PWR_FLT_PVNN               <= LOW;
                oCPU_PWR_FLT_EHV_CPU            <= LOW;

                oCPU_PWR_FLT                    <= LOW;
                oMEM_PWR_FLT                    <= LOW;
            end else begin                                              // Detect VR failures, VR PWRGD de-asserted but not in power down flow
                rPWRGD_PVCCFA_EHV_FIVRA_CPU     <= iPWRGD_PVCCFA_EHV_FIVRA_CPU;
                rPWRGD_PVCCINFAON_CPU           <= iPWRGD_PVCCINFAON_CPU;
                rPWRGD_PVCCIN_CPU               <= iPWRGD_PVCCIN_CPU;
                rPWRGD_PVCCD0_HV_MEM            <= iPWRGD_PVCCD0_HV_CPU;
                rPWRGD_PVCCD1_HV_MEM            <= iPWRGD_PVCCD1_HV_CPU;
				rPWRGD_PVNN_MAIN_CPU            <= iPWRGD_PVNN_MAIN_CPU;
				rPWRGD_PVCCFA_EHV_CPU           <= iPWRGD_PVCCFA_EHV_CPU;

                oCPU_PWR_FLT_PVCCD0_HV          <= (oFM_PVCCD_HV_CPU_EN && rPWRGD_PVCCD0_HV_MEM && !iPWRGD_PVCCD0_HV_CPU) ? HIGH: oCPU_PWR_FLT_PVCCD0_HV;
                oCPU_PWR_FLT_PVCCD1_HV          <= (oFM_PVCCD_HV_CPU_EN && rPWRGD_PVCCD1_HV_MEM && !iPWRGD_PVCCD1_HV_CPU) ? HIGH: oCPU_PWR_FLT_PVCCD1_HV;
                oCPU_PWR_FLT_EHV_FIVRA_CPU      <= (oFM_PVCCFA_EHV_FIVRA_CPU_EN && rPWRGD_PVCCFA_EHV_FIVRA_CPU && !iPWRGD_PVCCFA_EHV_FIVRA_CPU) ? HIGH: oCPU_PWR_FLT_EHV_FIVRA_CPU;
                oCPU_PWR_FLT_PVCCINFAON_CPU     <= (oFM_PVCCINFAON_CPU_EN && rPWRGD_PVCCINFAON_CPU&& !iPWRGD_PVCCINFAON_CPU) ? HIGH: oCPU_PWR_FLT_PVCCINFAON_CPU;
                oCPU_PWR_FLT_PVCCIN             <= (oFM_PVCCIN_CPU_EN && rPWRGD_PVCCIN_CPU && !iPWRGD_PVCCIN_CPU) ? HIGH: oCPU_PWR_FLT_PVCCIN;

                oCPU_PWR_FLT_PVNN               <= (oFM_PVNN_MAIN_CPU_EN && rPWRGD_PVNN_MAIN_CPU && !iPWRGD_PVNN_MAIN_CPU) ? HIGH: oCPU_PWR_FLT_PVNN;
                oCPU_PWR_FLT_EHV_CPU            <= (oFM_PVCCFA_EHV_CPU_EN && rPWRGD_PVCCFA_EHV_CPU && !iPWRGD_PVCCFA_EHV_CPU) ? HIGH: oCPU_PWR_FLT_EHV_CPU;

                oCPU_PWR_FLT                    <= (oCPU_PWR_FLT_EHV_FIVRA_CPU || oCPU_PWR_FLT_PVCCINFAON_CPU || oCPU_PWR_FLT_PVCCIN || oMEM_PWR_FLT) ? HIGH: oCPU_PWR_FLT;
                oMEM_PWR_FLT                    <= (oCPU_PWR_FLT_PVCCD0_HV || oCPU_PWR_FLT_PVCCD1_HV) ? HIGH : oMEM_PWR_FLT;
            end
        end
    end

/*************************************************************************************************************
 * Instances                                                                                                 *
 *************************************************************************************************************/
    // 500-usec watchdog, when enable it, will counter if stay at certain stage for more than 500 usec
    counter2 #(.MAX_COUNT(T_500uS_2M))
        ForceOff_500usDly (
                           .iClk      ( iClk            ),
                           .iRst_n    ( iRst_n          ),
                           .iCntRst_n ( wCNT_RST_N      ),
                           .iCntEn    ( wCNT_RST_N      ),
                           .iLoad     ( !wCNT_RST_N     ),
                           .iSetCnt   ( T_500uS_2M[9:0] ),
                           .oDone     ( wDLY_500uS      ),
                           .oCntr     (                 )
                          );
   
    // 100-msec watchdog, started when certain VR enable signal de-asserted
    delay #(.COUNT(T_100mS_2M))
        Timer100ms (
                    .iClk    ( iClk             ),
                    .iRst    ( iRst_n           ),
                    .iStart  ( wStart100msTimer ),
                    .iClrCnt ( 1'b0             ),
                    .oDone   ( wDoneTimer100ms  )
                   );
endmodule
